1. Field of the Invention
An object of the present invention is a memory in integrated circuit form with an accelerated reading cycle. This acceleration is due to a more powerful and faster pre-charging of the bit lines. The invention can be applied more particularly in the field of EPROM memories or in that of EEPROM memories, where the memory cell has a floating gate transistor as its memorizing element.
The memory cells of a memory are organized in matrix form at the intersections of rows and columns: the rows are said to be bit lines and the columns are word lines. To gain access to the information contained in a memory cell, decoders are used to select a bit line and a word line that are characteristic of the memory cell to be read. The selection of a memory cell is aimed at connecting it to a current sensing circuit known as a sense amplifier. Depending on its state of programming, the memory cell formed by the floating gate transistor then behaves as an open circuit or as a resistor. If it is a resistor, the bit line to which it belongs is connected, at the moment of its selection, to the ground of the circuit of the memory. Under these conditions, a discharge current may flow in the bit line. On the contrary, if it is an open circuit, the voltage applied to the bit line is preserved, and the sense amplifier does not detect the passage of short-circuit current. Consequently, a static electrical state, namely the electrical state programmed in the memory, has been thus converted into a dynamic electrical state variable in time. This change in state is then used in the different circuits connected to the memory.
2. Description of the Prior Art
The process, as just described, requires the pre-charging of the bit line at a certain voltage, before the selection of the memory cell concerned by the bit line. The sense amplifier is connected to the bit line at least at the end of this pre-charging operation. As soon as the concerned word line is activated, the short-circuit phenomenon or the open circuit phenomenon occurs, and the current flows or does not flow in the sense amplifier. Since the sense amplifier is thus connected beforehand to the bit line, methods have been developed and perfected for pre-charging the bit line. In these methods, the bit line pre-charging circuit is integrated with the sense amplifier. A sense amplifier D of this type can be recognized in FIG. 1. This figure concerns the invention, but also shows the state of the art with the sense amplifier D. With a circuit such as this, it becomes possible to pre-charge the bit lines which can be likened, at the time of pre-charging or reading, to an RC circuit, at the end of a period substantially equal to 50 ns.
This standard pre-charging circuit works as follows: at the outset, the bit line represented by any one of the RC circuits to the left of figure is connected to the point C. The potential of the bit line is at V.sub.SS, equal to zero volts. To pre-charge the bit line, the sense amplifier D is activated, for example by means of a signal VREF that is applied to the gate of a p type transistor P.sub.1. The transistor P.sub.1 is connected firstly to V.sub.cc (supply voltage) and, secondly, to a point A. The activation by the signal VREF is aimed at taking A to the value of V.sub.cc. When this is done, an n type transistor N.sub.1, which is connected by its drain to the potential Vcc and receives the potential of the point A at its gate, becomes conductive. This is also true for a transistor NAT.sub.2 which receives the potential of the point A at its gate, and has its drain also connected to Vcc by the turning on of a p type transistor P.sub.2. The transistor P.sub.2 too is controlled by the control potential VREF. The transistors N.sub.1 and NAT.sub.2 then charge the bit line to which they are connected at the point C by their source. The voltage of the point C rises. Since the voltage of the point C rises, an n type transistor N.sub.2 is prompted to become conductive. The transistor N.sub.2 is cascade-mounted, between the transistor P.sub.1 and an n type transistor NAT.sub.1, between Vcc and the ground. The transistor N.sub.2 receives the voltage of the point C at its gate. The transistor NAT.sub.1 is mounted as a diode because of the connection of its gate to its drain.
A reverse feedback then acts on the voltage of the point A. The voltage of the point A therefore stabilizes at an intermediate voltage determined by the transistors P.sub.1, N.sub.2 and NAT.sub.1. Owing to the fact that its gate is short-circuited to its drain, the transistor NAT.sub.1 behaves like a diode: it is used to increase the voltage of the point A as soon as a current flows in the transistor N.sub.2 and in the transistor NAT.sub.1. The voltage at the point C is then equal to the conduction threshold voltage V.sub.T of the transistor N.sub.2 (V.sub.TN2) added to the conduction threshold voltage of the transistor NAT.sub.1 (V.sub.TNAT1), that is, 1.2 volts.
Indeed, if the voltage at C rises, the transistors P.sub.2 and NAT.sub.1 tend to be more conductive and make the voltage fall at the point A. The voltage C then decreases naturally, by the fact that the transistors N.sub.1 and NAT.sub.2 then become less conductive. By contrast, if the voltage at C drops, these two transistors tend to be less conductive and the reverse phenomenon occurs. Thus, the transistors N.sub.1 and NAT.sub.2 charge the bit line until the voltage at C has reached this value.
At the time of reading, the bit line to be read may or may not be considered to be a resistor of the point C grounded, depending on the state of programming of the memory cell to be read in this bit line. When there is a link to the ground, the voltage at the point C drops sharply and the transistor NAT.sub.2 has to let through a lot
of current. As the control of the transistor NAT.sub.2 has not varied, since the voltage of the point A remains at the same potential during the reading operation, the result thereof is that the voltage of an intermediate point B between the transistor P.sub.2 and the transistor NAT.sub.2 rises again sharply. By contrast if, at the time of the reading, no "short circuit" is detected, the voltage at the point B remains at its initial low level. An output inverter assembly P.sub.4 -N.sub.4 connected to this point B flips over or does not flip over, respectively, as a function of this reading. The output S respectively delivers a high signal (V.sub.cc) or a low signal (V.sub.ss).
The slowness of the charging of the bit lines comes essentially from the reverse feedback circuit NAT.sub.2 -N.sub.2 -NAT.sub.1. Given the technology implemented to date, the rising time of the voltage, at the point C, to the value of 1.2 volts is of the order of 50 ns, depending on the number of cells per bit line. This duration is far too long.
Besides, it can be noted that each bit line or, rather, each group I to J of bit lines should be connected to a specific sense amplifier. In a particular assembly, each bit line is connected to 512 memory cells. In this example, where the reading is in eight bits, eight groups of bit lines are set up and, in each group of bit lines, it is possible to have 64 bit lines (I=1; J=64). In each group of bit lines, we thus have 64 bits of the same weight corresponding to 64 different words. Thus, for each group of bit lines, there is a sense amplifier such as the sense amplifier D. This assembly calls for efficient mastery over the manufacturing process since the bit lines in each group are charged by different charge circuits. If, under these conditions, there is a disparity in the characteristics of the transistors NAT.sub.2, NAT.sub.1 or N.sub.2, it could also lead to reading aberrations.
An object of the invention is to overcome these drawbacks by proposing a bit line pre-charging circuit that is independent of the sense amplifier itself and is far more powerful. Besides, to prevent manufacturing disparities and also to limit the space occupied by the layout entailed in an additional, more powerful pre-charging circuit, provision has been made for short-circuiting all the bit lines to be pre-charged, together, at the time of pre-charging. As a result, there is obtained a pre-charging that is simultaneously fast, identical for all the lines and without any notable additional bulkiness.